For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, leading to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, tri-gate transistors may be electrically coupled to form complementary metal-oxide-semiconductor (CMOS) devices. CMOS devices include complementary pairs of N-type and P-type transistors that may be coupled together to perform logic operations.
In order to optimize the performance of the CMOS, it is often necessary to form the N-type and P-type transistors with different semiconductor materials. Typically, this is done by forming an island of a second semiconductor material in a first semiconductor substrate. For example, in FIG. 1A an opening 110 is etched into a silicon substrate 105. Thereafter, as illustrated in FIG. 1B, a second semiconductor material is epitaxially grown in the opening 110 to form an island region 112. A plurality of fins 120 may then be patterned into the substrate 105 and the island region 112 with a dry-etching process, as illustrated in FIG. 1C. However, as the critical dimension of the fins continues to be reduced, the dry-etching process begins to create problems.
Anisotropic dry-etching processes, such as those used to form high aspect ratio fins, typically include a combination of ion-bombardment and passivation. The passivation layer forms over the exposed surfaces, and the ion bombardment removes the passivation layer and the material being etched from the exposed planar surfaces. As such, the dry-etching process exposes the semiconductor material to a passivating species and is bombarded by ions. Accordingly, the dry-etching process may introduce impurities and generate surface defects in the etched fin that negatively impact the performance of tri-gate transistor devices made with the fins 120. It has been found that III-V semiconductor materials are particularly vulnerable to forming surface defects when exposed to dry-etching processes. Therefore, when an island region is formed with a III-V semiconductor material, the resulting fins formed with a dry-etching process may have poor performance characteristics compared to the fins formed in other portions of the semiconductor substrate.